Design of Radix¡M16 Booth Pipeline Multiplier
Liang Feng1£¬Shao Zhibiao1£¬Liang Jin2
£¨1£®School of Electronics and Information Engineering£¬Xi'an¡¡Jiaotong¡¡University£¬Xi'an
710049£¬hina£»
2£®School of Mechanical Engineering£¬Xi'an¡¡Jiaotong¡¡University£¬Xi'an 710049£¬China£©
Abstract£ºA novel 32¡Á32-b highª²speed pipeline multiplier structure is designed£®
Taking advantages of the merits of redundant Booth encoding and modified Booth encoding£¬
the novel Radix-16 Booth algorithm of the structure can simply and quickly generate
complicated multiples£® The designed multiplier has only 9 partial products£¬ which
effectively reduces the size and delay of compression array£® By optimizing the
compression array and the 64-b CLA £¨carryª²lookahead£© adder in the critical path of
pipeline£¬ this multiplier can effectively reduce the delay and area£¬ too£® The field
programmable gate array £¨FPGA£© simulation shows that compared to the multiplier with
Radix-8 Booth algorithm£¬ the speed of this multiplier is increased by 11£¥ and its
hardware resource is reduced by 3£¥£®
Keywords£ºmultiplier£» Booth algorithm£» pipeline£» compression array