Hu Lin,Shao Zhibiao
(School of Electronics and Information Engineering,Xi'an Jiaotong University,Xi'an 710049,China)
Abstract:Using single pulse control an advanced parallel mode ROM architecture was developed.This design architecture reduced the voltage swing of the bit-line,thus the operating speed is improved and the switching power is decreased.The interfacing to other blocks in system on a chip(SOC) also benefited from its regular periphery. It is well suited for embedded ROM within SOC due to its excellent speed and power performance.The 1 k¡Á28 bit mask-ROM designed by 0.6 ¦Ìm CMOS technology was integrated into the microprocessor unit. The simulation and fabrication results show that the 1k¡Á28bit mask-ROM has read access time of 12 ns and power dissipation of about 0.82 mW£¯MHz, and area of 0.64¡Á0.63 mm2.
Keywords:embedded ROM;single pulse control;parallel mode