Mei Kuizhi,Zheng Nanning,Lan Xuguang,Yao Ji
(The Institute of Artificial Intelligence and Robotics,Xi'an Jiaotong University,Xi'an 710049,China)
Abstract: Focusing on the problem of path waiting or circular which existed in updating of context (CX) table and the renorme and byteout in the realization of the conventional arithmetic encoder in JPEG2000, a four-step pipeline architecture is employed to design an arithmetic encoder on FPGA platform to get high speed encoding. A new method of updating CX table is proposed; and a new circuit with short delay is implemented to detect the left zeros of A-register. Multiplexers are adopted to accelerate the left shift operation, and parallel processing based on data dependency is used to optimize RTL(Register Transfer Language) code to shorten the main critical path. Experimental result shows that the encoder can work up to 107.91 MHz on Altera's EP1S25B672C7.
Keywords: arithmetic encoder; pipeline;critical path